1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to control and status registers (CSRs) included in integrated circuits.
2. Description of the Related Art
A typical computer system includes a central processing unit (CPU) coupled to one or more peripheral devices (e.g., disk drives and printers). The CPU typically monitors and controls the peripheral devices via addressable control and status registers (CSRs) within the devices. For example, in order to determine the state of a peripheral device, the CPU may read a status value from an address of a status register within the device. In order to configure or control functions of the device, the CPU may write a control value to an address assigned to a control register within the device. It is noted that the CPU itself may include CSRs and may be monitored and controlled via the CSRs.
The CSRs of a device are typically formed with other device logic upon a single integrated circuit (IC). As IC fabrication technology has improved, the ability to integrate more and more functions onto single silicon substrates has increased. As a result, the number of functions performed by devices has also increased. In turn, the number of CSRs within the devices has necessarily increased. In fact, some devices now include hundreds of CSRs. It is also noted that shrinking IC device geometries have also allowed operating speeds of devices to increase.
Given the number of CSRs that may be present on a given IC, a significant amount of power may be consumed by the CSRs. As operating speeds increase, power consumption also tends to increase. Consequentially, it is desirable to be able to reduce the power consumed by the CSRs on a given IC.
Typical power saving techniques tend to focus control the IC as a whole or control large numbers of devices within the IC. For example, one way to reduce power consumption is to turn off the IC or reduce the operating speed of the IC during times when the IC is not being used or is not experiencing heavy demand. However, since these techniques apply to the IC as a whole, they may miss opportunities to reduce the power consumption of individual devices within the IC. Consequentially, it is desirable to reduce the power consumed by individual CSRs within an IC, even when the rest of the IC is not turned off or operating at a reduced speed.
Various embodiments of systems and methods for reducing the power consumption of CSRs (Control and Status Registers) within an integrated circuit (IC) are disclosed. In one embodiment, an integrated circuit includes a plurality of CSRs. Each CSR includes one or more flip-flops that are used to store one or more bits of control and/or status information for an associated device on the IC. The IC also includes one or more clock gates. Each clock gate is coupled to provide a gated clock signal to one or more of the flip-flops in a respective one of the CSRs. Each clock gate is configured to output a clock signal as the gated clock signal if a clock enable signal that corresponds to the respective CSR is asserted. The IC also includes one or more clock gating units. Each clock gating unit is configured to generate the clock enable signal for a respective one of the CSRs. For example, a first clock gating unit is configured to assert the clock enable signal for a first one of the CSRs in response to detecting a software update to the first CSR.
In one embodiment, each clock gate may be integrated into a respective flip-flop. Accordingly, each flip-flop may have a clock enable input and a clock signal input. The first controller may detect a software update to the first CSR by detecting an indication (e.g., a destination address equal to the address of the first CSR) that the first CSR is the destination of a write command. In some embodiments, some of the controllers may be configured to assert the clock enable signal for a respective CSR in response to detecting a hardware update to that CSR.
In some embodiments, a method of reducing power consumption of an integrated circuit comprising a plurality of CSRs may involve deasserting a first clock enable signal associated with a first CSR and deasserting a second clock enable signal to a second CSR. When their respective clock enable signals are deasserted, the first and second CSRs may consume a reduced amount of power. However, the first and second CSRs may not be able to be updated while their respective clock enable signals are deasserted. Thus, the method may also involve subsequently detecting a software update to the first CSR and, in response, asserting the first clock enable signal associated with the first CSR. In response to asserting the clock enable signal, a clock signal may be provided to the first CSR so that the software update can occur. The first clock enable signal is asserted independently of the second clock enable signal.
In another embodiment, an IC includes a plurality of means for storing control and status information, where each of the means for storing control and status information cannot be updated unless a respective clock enable signal is asserted. The IC may also include one or more means for detecting a software update to a respective one of the means for storing control and status information. Each means for detecting the software update controls the respective clock enable signal for the respective one of the means for storing control and status information. Each means for detecting the software update asserts the respective clock enable signal in response to detecting a software update to the respective one of the means for storing control and status information.